The layout design, which defines the functionality of the circuit, is present at the start of the fabrication process of highly integrated electronic circuits for semiconductor components (e.g., DRAM). The layout specifies the physical implementation of the circuit, e.g., on a silicon wafer.
Known methods for fabricating the circuit on the wafer are based on lithography, i.e., a process that involves, among other steps, making an image of the circuit layout first on a mask and then exposing the mask to produce an image on the wafer.
The chip is fabricated in many steps. Each of the fabrication steps has an intrinsic inaccuracy, which ideally should be taken into account back in the layout design. Rules (known as design or layout rules) are provided for this purpose, which must be observed in the layout design in order to ensure that the layout can actually be fabricated later. For example, such layout rules may define the minimum distance between two transistors or the width of metal tracks.
Once the layout design is finished, the layout is checked on the basis of these layout rules (DRC design rule check), and corrected if necessary. This step is called verification and is performed by computers. Since the components of an integrated circuit are represented in the layout by polygons, the layout rules relate to the geometrical properties of polygons and to their geometrical relationships with one another. For example, a diode comprising a p-type and an n-type region is represented in the layout by touching rectangles.
In the simplest case, a layout rule can relate to a single dimension. Complex layout rules, on the other hand, relate a large number of dimensions to each other.
Complex layout rules mostly have to be formulated using numerous instructions, thereby increasing the computing time to an unwanted degree. Some layout rules are even formulated so that the instruction set of the verification software is not adequate, and “dummy errors” (supposed errors) must be tolerated. Dummy errors mean that the geometrical rules no longer apply in all areas of a chip layout.
There is also the problem that when there are many complex processes, the number of dummy errors increases so steeply that the “true” errors are no longer identified.
Another problem is that in practice, verification of a layout must be performed in some areas using a lithography simulation, because verification using conventional DRC is no longer sufficient. Thus, two methods that are not integrated with each other are required for verification, which drives up verification costs. In addition, it is no longer possible to prove unequivocally that a layout is correct, because different verifications are used.
These problems mean that manual inspections or other “exceptional operations” need to be performed. Hand-drawn wafer layers or cataloguing of known error patterns are used for this.